Design of Ultra Low Power SRAM Cell

In order to achieve a longer battery life suppression of energy consumption is vital. A demand for design methods for less energy consumption is increasing. The subthreshold scaling can reduce energy per cycle significantly by the scaling of supply voltage (VDD) below threshold voltage (Vth). Threshold voltage of CMOS technology represents the value of the gate-source voltage when the current in a MOS transistor starts to increase significantly since the conduction layer just begins to appear. MOS transistor can also function correctly with a supply voltage below its threshold voltage (Vth), which is referred to as sub-threshold operation or weak-inversion of a transistor. The circuits that work under a supply voltage in the sub-threshold range are named sub-threshold circuits. In ultra low power design, the operation of circuit in subthreshold regime is most important and the SRAM circuit has the limitation of read disturb. In order to eliminate this limitation The Single-ended design is used. In this paper we propose the single-ended with dynamic feedback control (SE-DFC) cell. In this paper focus is mainly on the stability of the cell which is affected by the process parameter variations. Various foundry technologies are used for the design of SE-DFC ram cell and the one with least power dissipation is proposed.